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1 hsp45256 binary correlator the intersil hsp45256 is a high-speed, 256 tap binary correlator. it can be con?gured to perform one-dimensional or two-dimensional correlations of selectable data precision and length. multiple hsp45256s can be cascaded for increased correlation length. unused taps can be masked out for reduced correlation length. the correlation array consists of eight 32-tap stages. these may be cascaded internally to compare 1, 2, 4 or 8-bit input data with a 1-bit reference. depending on the number of bits in the input data, the length of the correlation can be up to 256, 128, 64, or 32 taps. the hsp45256 can also be con?gured as two separate correlators with window sizes from 4 by 32 to 1 by 128 each. the mask register can be used to prevent any subset of the 256 bits from contributing to the correlation score. the output of the correlation array (correlation score) feeds the weight and sum logic, which gives added ?exibility to the data format. in addition, an offset register is provided so that a preprogrammed value can be added to the correlation score. this result is then passed through a user programmable delay stage to the cascade summer. the delay stage simpli?es the cascading of multiple correlators by compensating for the latency of previous correlators. the binary correlator is con?gured by writing a set of control registers via a standard microprocessor interface. to simplify operation, both the control and reference registers are double buffered. this allows the user to load new mask and reference data while the current correlation is in progress. features ? recon?gurable 256 stage binary correlator ? 1-bit reference x 1, 2, 4, or 8-bit data ? separate control and reference interfaces ? 25.6, 33mhz versions ? con?gurable for 1-d and 2-d operation ? double buffered mask and reference ? programmable output delay ? cascadable ? standard microprocessor interface applications ? radar/sonar ? spread spectrum communications ? pattern/character recognition - error correction coding block diagram ordering information part number temp. range ( o c) package pkg. no. hsp45256jc-25 0 to 70 84 ld plcc n84.1.15 hsp45256jc-33 0 to 70 84 ld plcc n84.1.15 hsp45256gc-25 0 to 70 85 ld pga g85.a hsp45256gc-33 0 to 70 85 ld pga g85.a HSP45256JI-25 -40 to 85 84 ld plcc n84.1.15 hsp45256ji-33 -40 to 85 84 ld plcc n84.1.15 256 tap correlation array control weight and sum mux delay cascade summer din0-7 dref0-7 dcont0-7 a0-2 casin0-12 auxout0-8 casout0-12 dout0-7 dout drefout cscore data sheet may 1999 file number 2814.4 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. http://www.intersil.com or 407-727-9207 | copyright ? intersil corporation 1999
2 pinouts 85 pin pga bottom view 85 pin pga top view a b c d e f g h j k l dref0 gnd txfr a2 dcont7 dcont1 dcont0 dcont3 aux aux aux out8 out7 out5 v cc dref2 a0 dcont dcont rlo ad clo ad oea aux aux aux 62 a1 dcont dcont gnd dref1 dref3 54 aux out2 casin casin casin casin casin casin gnd casout 8 casout 5 casout casout 0 2457 10 11 casin6 casin1 casin casin3 gnd casout 10 casout casout casout 4 casout 1 casout 2 9 dref4 auxout auxout dref5 0 1 din0 dref7 din1 dout6 dout5 v cc din3 din2 dout4 dref6 dout7 dout3 dout0 dout1 dout2 din4 din6 din5 gnd din7 casout 12 v cc clk casin0 casin casin oec casout 11 casout index pin 8 12 out6 out4 out3 9 7 1234567891011 3 a b c d e f g h j k l 2 17 3 4 5 6 8 9 10 11 clk din7 din4 din0 dref dref dref gnd dref casin 2 0 2 5 6 dref 3 v cc casin casin din3 dref dref v cc gnd din5 casin 4 1 0 1 4 dref 7 index pin din6 din2 din1 txfr casin r casin 5 lo ad 3 a2 c casin casin 7 6 lo ad casin a1 a0 dcont casin casin 10 9 8 7 dcont dcont dcont casin cas casin 12 11 1 6 5 out2 oec dcont dcont dcont cas cas 3 2 4 out out1 dcont cas oea cas 0 out3 out4 dout0 dout v cc cas aux cas 4 out5 out6 aux out6 out8 gnd dout dout gnd dout cas cas aux aux aux gnd 7 6 out7 out9 out1 out4 out7 dout2 dout dout cas cas cas aux aux aux aux cas 3 5 out8 out10 out11 out12 out0 out2 out3 out5 hsp45256
3 84 pin plcc top view pinouts (continued) 111098765432184838281807978777675 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 v cc rlo ad gnd txfr clo ad a2 a1 a0 dcont7 dcont6 dcont5 dcont4 dcont3 dcont2 dcont1 dcont0 oea auxout8 auxout7 auxout5 auxout6 casin1 casin0 gnd clk v cc din7 din6 din5 din4 din3 din2 din1 din0 dref7 dref6 dref5 dref4 dref3 dref2 dref1 dref0 casout8 casout9 casout10 casout11 gnd casout12 dout0 dout1 dout2 dout3 dout4 v cc dout5 dout6 dout7 auxout0 auxout1 auxout2 auxout3 gnd auxout4 casin2 casin3 casin4 casin5 casin6 casin7 casin8 casin9 casin10 casin11 casin12 oec# casout0 casout1 casout2 casout3 casout4 casout5 gnd casout7 casout6 hsp45256
4 pin descriptions symbol plcc pin number type description v cc 16, 33, 63 the +5v power supply pin. gnd 14, 35, 55, 70, 77 ground. din0-7 17-24 i the din0-7 bus consists of eight single data input pins. the assignment of the active pins is determined by the con?guration. data is loaded synchronous to the rising edge of clk. din0 is the lsb. dout0-7 60-62, 64-68 o the dout0-7 bus is the data output of the correlation array. the format of the output is de- pendent on the window con?guration and bit weighting. dout0 is the lsb. clk 15 i system clock. positive edge triggered. casin0-12 1-13 i casin0-12 allows multiple correlators to be cascaded by connecting casout0-12 of one correlator to casin0-12 of another. the casin bus is added internally to the correlation score to form casout. casin0 is the lsb. casout0-12 69, 71-76, 78-83 o casout0-12 is the output correlation score. this value is the delayed sum of all the 256 taps of one chip and casin0-12. when the part is con?gured to act as two independent cor- relators, casout0-8 represents the correlation score for the ?rst correlator while the sec- ond correlation score is available on the auxout0-8 bus. in this con?guration, the cascading feature is no longer an option. casout0 is the lsb. oec 84 i oec is the output enable for casout0-12. when oec is high, the output is three-stated. processing is not interrupted by this pin (active low). txfr 36 i txfr is a synchronous clock enable signal that allows the loading of the reference and mask inputs from the preload register to the correlation array. data is transferred on the rising edge of clk while txfr is low (active low). dref0-7 25-32 i dref0-7 is an 8-bit wide data reference input. this is the input data bus used to load the reference data. rlo ad going active initiates the loading of the reference registers. this in- put bus is used to load the reference registers of the correlation array. the manner in which the reference data is loaded is determined by the window con?guration. if the window con- ?guration is 1 x 256, the reference bits are loaded one at a time over dref7. when the hsp45256 is con?gured as a n8x32array,the data is loaded into all stages in parallel. in this case, dref7 is the reference data for the ?rst stage and dref0 is the reference data for the eighth stage. the contents of the reference data registers are not affected by chang- ing the window con?guration. dref0 is the lsb. rlo ad 34 i rlo ad enables loading of the reference registers. data on dref0-7 is loaded into the pre- load registers on the rising edge of rlo ad. this data is transferred into the correlation array by txfr (active low). dcont0-7 41-48 i dcont0-7 is the control data input which is used to load the mask bit for each tap, as well as the con?guration registers. the mask data is sequentially loaded into the eight stages in the same manner as the reference data. dcont0 is the lsb. clo ad 37 i clo ad enables the loading of the data on dcont0-7. the destination of this data is con- trolled by a0-2 (active low). a0-2 38-40 i a0-2 is a 3-bit address that determines what function will be performed when clo ad is ac- tive. this address bus is set up with respect to the rising edge of the load signal, clo ad. a0 is the lsb. auxout0-8 50-54, 56-59 o auxout0-8 is a 9-bit bus that provides either the data reference output in the single corre- lation con?guration or the 9-bit correlation score of the second correlator, in the dual corre- lator con?guration. when the user programs the chip to be two separate correlators, the score of the second correlator is output on this bus. when the user has programmed the chip to be one correlator, auxout0-7 represents the reference data out, with the state of auxout8 unde?ned. auxout0 is the lsb. oea 49 i the oea signal is the output enable for the auxout0-8 output. when oea is high, the out- put is disabled. processing is not interrupted by this pin (active low). hsp45256
5 block diagram note: all registers clocked with clk unless otherwise speci?ed. correlator block diagram mask config off al off am dela y offbl offbm decode clo ad a(2:0) 32 tap correlator stage rlo ad txfr din7 dref7 do7 ro7 mux array + co7 correlation score out din6 dref6 do6 ro6 co6 32 tap correlator stage do0 ro0 co0 ro7 din0 dref0 ro1 mr7 mr6 mr0 data out do7 do1 r e g > r e g > r e g > r e g > r e g > 32 tap correlator stage + r e g > r e g > + r e g > r e g > r e g > r e g > r e g > dcont(7:0) ro7 ro6 ro0 reference out casin(12:0) dout(7:0) oea oec casin(12:0) oea oec (000) (001) 8 6 config(4:0) tc tc 5 config(4:0) config(4:0) clk data out r e g > hsp45256
6 note: all registers clocked with clk unless otherwise speci?ed. block diagram (continued) weight sum offset register a programmable delay offset register b auxout(8:0) cascade register + casin(12:0) ro(0-7) oea oec casout(12:0) rlo ad off al off am dela y offbl offbm r e g > r e g > dela y r e g > r e g > r e g > co7 co6 co0 correlation score out reference out r e g > r e g > r e g > r e g > r e g > r e g > dout(7:0) dout(7:0) oea oec (100) 4 (010) (011) (101) (110) 5 8 1 8 config(4:0) config(4:0) hsp45256
7 functional description the correlation array consists of eight 32-bit stages. the ?rst stage receives data directly from input pin din7. the other seven stages receive input data from either an external data pin, din0-6, or from the shift register output of the previous stage, as determined by the con?guration register. when the part is con?gured as a single correlator the sum of correlation score, offset register and cascade input appears on casout0-12. delayed versions of the data and reference inputs appear on dout0-7 and auxout0-7, respectively. the input and output multiplexers of the correlation array are controlled together; for example, in a 1 x 256 correlation, the input data is loaded into din7 and the output appears on dout7. the con?guration of the data bits, the length of the correlation (and in the two-dimensional data, the number of rows), is commonly called the correlation window. a top level block diagram of the single correlator con?guration is shown in figure 1. compare the single correlator con?guration data output and correlation output to the top level block diagram of the dual correlator con?guration shown in figure 2. correlator array the core of the hsp45256 is the correlation array, which consists of eight 32-tap stages. a single correlator cell consists of an xnor gate for the individual bit comparison; i.e., if the data and reference bits are either both high or both low, the output of the correlator cell is high. figure 3 details the circuitry of a single correlation cell and figure 4 shows the timing for that single correlation cell. in addition, two latches, one for the reference and one for the control data path are contained in this cell. these latches are loaded from the preload registers on the rising edge of clk when txfr is low so that the reference and mask values are updated without interrupting data processing. the mask function is implemented with an and gate. when a mask bit is a logic low, the corresponding correlator cell output is low. 8 32-bit correlators din(7:0) dref(7:0) dout(7:0) sum weight and corr score sum delay sum offa casin(12:0) casout(12:0) auxout(7:0) figure 1. single correlator configuration ? ? ? ? ? ? ? ? ? ? ? ? figure 2. dual correlator configuration ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 4 32-bit correlators din(7:4) dref(7:4) dout(7:4) sum weight and corr score sum delay sum offa casout(8:0) = 0000 casin(12:0) 4 32-bit correlator din(3:0) dout (3:0) dref(3:0) sum corr score weight and sum offb auxout(8:0) correlator #1 correlator #2 hsp45256
8 the function performed by one correlation cell is: (d i,n xnor r i,n ) and m i,n where: d i,n = bit i of data register n r i,n = bit i of reference register n m i,n = bit i of mask register n the reference and mask bits are loaded sequentially, n bits at a time, where n depends on the current con?guration (see tables 2 and 9). new reference data is loaded on the rising edge of rlo ad and new mask data is loaded on the rising edge of clo ad. the mask and reference bits are stored internally in shift registers, so that the mask and reference information that was loaded most recently will be used to process the newest data. when new information is loaded in, the previous contents of the mask and reference bits are shifted over by one sample, and the oldest information is lost. there are no registers in the multiplexer array (see block diagram), so the data on dout0-7 corresponds to the data in the last element of the correlation array. when monitoring dout0-7, auxout0-8, and refout0-7, only those bits listed in table 9 are valid. figure 3. correlation cell block diagram figure 4. correlation cell timing diagram r e g > rload dref r e g > dcont cload drefout dcontout r e g > txfr r e g > clk data dataout corout a b r e g > (mask) rload dref dcont cload txfr clk data data control a b dr8 dr7 dr6 dr5 dr4 dr3 dr2 dr1 dr0 dr7 dr6 dr5 dr4 dr3 dr2 dr1 dr0 dr7 dr6 dr5 dr4 dr3 dr2 dr1 dr0 dr-1 d7 d6 d5 d4 d3 d2 d1 d0 d-1 hsp45256
9 weight and sum logic the weight and sum logic provides the bit weighting and the ?nal correlator score from the eight stages of the correlation array. for a 1 x 256 1-d con?guration, the outputs of each of the stages are given a weight of 1 and then added together. in a 8 x 32 (8-bit data) con?guration, the output of each stage will be shifted so that the output data represents an 8-bit word, with stage seven being the msb. the 13-bit offset register is loaded from the control data bus. its output is added to the correlation score obtained from the correlator array. this sum then goes to the programmable delay register data input. when the chip is con?gured as dual correlators, the user has the capability of loading two different offset values, one for each of the two correlators. the programmable delay register sets the number of pipeline stages between the output of the weight and sum logic and the input of the cascade summer. this delay register is used to align the correlation scores of multiple correlators in hsp45256 cascaded con?gurations (see applications section). the number of delays is programmable from 1 to 16, allowing for up to 16 correlators to be cascaded. when the hsp45256 is con?gured as dual correlators, the delay must be set to 0000, which speci?es a delay of 1. cascade summer the cascade summer is used for cascading several correlator chips together. the value present on this bus represents the correlation score from the previous hsp45256 that will be summed with the current score to provide the ?nal correlation score. when several correlator chips are cascaded, the casout0-12 of each correlator is connected to the casin0-12 of the next correlator in the chain. the casin0-12 of the ?rst chip is tied low. the following function represents the correlation score present on casout0-12 of each correlator: casout(n) = (w7 x co7)(n-delay) + (w6 x co6)(n-delay) + (w5 x co5)(n-delay) + (w4 x co4)(n-delay) + (w3 x co3)(n-delay) + (w2 x co2)(n-delay) + (w1 x co1)(n-delay) + (w0 x co0)(n-delay) + offset (n-delay) + casin. where: co0-co7 are the correlation score outputs out of the correlation stages; w0-w7 is the weight given to each stage; n-delay represents the delay on the weighted and summed correlation score through the programmable delay register; offset is the value programmed into the offset register; casin is the cascade input. control registers the 3-bit address value, a0-2, is used to determine which internal register will be loaded with the data on dcont0-7. the function is initiated when clo ad is brought low, and the register is loaded on the rising edge of clo ad. table 1 indicates the function associated with each address. tables 2 - 8 de?ne the function of the bits in each of the control registers. table 1. address mapping a2 a1 a0 destination 0 0 0 mask register 0 0 1 configuration register 0 1 0 offset register a-most significant bits 0 1 1 offset register a-least significant bits 1 0 0 programmable delay register 1 0 1 offset register b-most significant bits 1 1 0 offset register b-least significant bits 1 1 1 reserved hsp45256
10 table 2. mask register destination address = 0 (000) bit positions function description 7-0 mask register bit enable mr(7:0): mask register. when mask register bit n = 1, the corresponding reference register bit is en- abled. mask register data is loaded from the dcont(7:0) bus into a holding register on the rising edge of cload and is written to the mask register on the rising edge of txfr. table 3. configuration register destination address = 1 (001) bit position function description 7-6 reserved reserved; program to zero. 5 tc con?gures correlator for twos complement input format, where the position of the msb is depends on the current con?guration. tc = 1 is twos complement; tc = 0 is offset binary. 4 config(4) config4: the state of config4 configures the hsp45256 as either one or two correlators. when config4 = 0, the hsp45256 is configured as one correlator with the correlation score available on casout0-12. when config4 = 1, the hsp45256 is configured as dual correlators with the first correlators score available on casout0-8 and the second score available on auxout0-8. when the chip is configured as dual correlators, the programmable delay must be set to 0000 for a delay of 1. 3-2 config(3:2): config(3:2): control the number of data bits to be correlated. see table 9. 1-0 config(1:0) config(1:0): config1 and config0 represent the length of the correlation window as indicated in table 9. table 4. ms offset register a destination address = 2 (010) bit position function description 7-5 reserved reserved. program to zero. 4-0 offset register a msb offa(12:8): most significant bits of offset register a. this is the register used in single correlator mode. table 5. ls offset register a destination address = 3 (011) bit position function description 7-0 offset register a lsb offa(7:0): least significant bits of offset register a. table 6. programmable delay register destination address = 4 (100) bit position function description 7-4 reserved reserved. program to zero. 3-0 programmable delay pdelay(3:0): controls amount of delay from the weight and sum logic to the cascade summer. the number of delays is 1-16, with pdelay = 0000 corresponding to a delay of 1 and pdelay = 1111 cor- responding to a delay of 16. hsp45256
11 table 7. ms offset register b destination address = 5 (101) bit position function description 7-1 reserved reserved. program to zero. 0 offset register b msb offb8: most significant bit of offset register b. in dual correlator mode, this register is used for the correlator whose output appears on the auxout pins. table 8. ls offset register b destination address = 6 (110) bit position function description 7-0 offset register b lsb offb0-7: least significant bits of offset register b. hsp45256
12 table 9. configuration setup configuration no. of corre- lators data bits rows length corre- lator active inputs active outputs output weighting 43210 din dref dout auxout casout co7 co6 co5 co4 co3 co2 co1 co0 00000 1 1 1 256 - 7 7 7 7 12-0 11111111 00001 1 1 2 128 - 7, 3 7, 3 7, 3 7, 3 12-0 11111111 00010 1 1 4 64 - 7, 5, 3, 17, 5, 3, 17, 5, 3, 17, 5, 3, 1 12-0 11111111 00011 1 1 8 32 - 7-0 7-0 7-0 7-0 12-0 11111111 00101 1 2 1 128 - 7, 3 7 7, 3 7, 3 12-0 22221111 00110 1 2 2 64 - 7, 5, 3, 17, 57, 5, 3, 17, 5, 3, 1 12-0 22221111 00111 1 2 4 32 - 7-07, 6, 5, 47-0 7-0 12-0 22221111 01010 1 4 1 64 - 7, 5, 3, 17 7, 5, 3, 17, 5, 3, 1 12-0 88224411 01011 1 4 2 32 - 7-0 7, 6 7-0 7-0 12-0 88224411 01111 1 8 1 32 - 7-0 7 7-0 7-0 12-0 128 8 32 4 64 2 16 1 10001 2 1 1 128 a b 7 3 7 3 7 3 - 8-0 12-0 - 1 - 1 - 1 - 1 - - 1 - 1 - 1 - 1 10010 2 1 2 64 a b 7, 5 3, 1 7, 5 3, 1 7, 5 3, 1 - 8-0 12-0 - 1 - 1 - 1 - 1 - - 1 - 1 - 1 - 1 10011 2 1 4 32 a b 7-4 3-0 7-4 3-0 7-4 3-0 - 8-0 12-0 - 1 - 1 - 1 - 1 - - 1 - 1 - 1 - 1 10110 2 2 1 64 a b 7, 5 3, 1 7 3 7, 5 3, 1 - 8-0 12-0 - 2 - 2 - 1 - 1 - - 2 - 2 - 1 - 1 10111 2 2 2 32 a b 7-4 3-0 7, 6 3, 2 7-4 3-0 - 8-0 12-0 - 2 - 2 - 1 - 1 - - 2 - 2 - 1 - 1 11011 2 4 1 32 a b 7-4 3-0 7 3 7-4 3-0 - 8-0 12-0 - 8 - 2 - 4 - 1 - - 8 - 2 - 4 - 1 hsp45256
13 during reference register loading, the 8-bits, dref0-7 are used as reference data inputs. the falling edge of rlo ad initiates reference data loading; when rlo ad returns high, the data on dref0-7 is latched into the selected correlation stages. the active bits on dref0-7 are determined by the current con?guration. the window configuration is determined by the state of control signals upon programming the control register. table 9 represents the programming information required for each window configuration. in table 9, note that the data listed for output weighting refers to the weights given to each of the correlation sum outputs (co0-7 in the block diagram). during initialization, the loading con?guration for the reference data is set by the user. table 9 shows the loading options. these load controls specify whether the reference data for a given stage comes from the shift register output of the previous stage or from an external data pin. applications there are 10 single correlator con?gurations possible with the hsp45256. there are six dual correlator con?gurations possible with the hsp45256. table 10 details the con?guration (bits x rows x length) and the maximum correlation sums of all combinations. single correlator con?gurations 1-bit data, single row, 256 samples con?guration a 1 x 256 (1-d con?guration) correlation requires only 1 hsp45256. to initialize the correlator, all the reference bits, control bits, the delay value of the variable delay, and the window con?guration must be speci?ed. table 11 details these settings for the 1-bit data, 256 samples con?guration. figure 5 illustrates the data ?ow through the correlator. table 10. correlation score formulas for single correlator configurations figure number configuration bits x rows x length highest possible total correla- tion score correlation score figure 5 1 x 1 x 256 256 cs=co7+co6+co5+co4+co3+co2+co1+co0 figure 6 1 x 2 x 128 256 cs=co7+co6+co5+co4+co3+co2+co1+co0 figure 7 1 x 4 x 64 256 cs=co7+co6+co5+co4+co3+co2+co1+co0 figure 8 1 x 8 x 32 256 cs=co7+co6+co5+co4+co3+co2+co1+co0 figure 9 2 x 1 x 128 384 cs=2(co7+co6+co5+co4)+co3+ co2+co1+co0 figure 10 2 x 2 x 64 384 cs=2(co7+co6+co5+co4)+co3+co2+co1+co0 figure 11 2 x 4 x 32 384 cs=2(co7+co6+co5+co4)+co3+co2+co1+co0 figure 12 4 x 1 x 64 960 cs=8(co7+co6)+4(co5+co4)+2(co3+co2)+co1+co0 figure 13 4 x 2 x 32 960 cs=8(co7+co6)+4(co5+co4)+2(co3+co2)+co1+co0 figure 14 8 x 1 x 32 8160 cs=128c07+64co6+32c05+16co4+8co3+4co2+2co1+co0 figure 15 1 x 1 x 128 1 x 1 x 128 128 cs=co7+co6+co5+co4cs=co31co2+co1+co0 figure 16 1 x 2 x 64 1 x 2 x 64 128 cs=co7+co6+co5+co4cs=co31co2+co1+co0 figure 17 1 x 4 x 32 1 x 4 x 32 128 cs=co7+co6+co5+corcs=co31co2+co1+co0 figure 18 2 x 1 x 64 2 x 1 x 64 192 cs=2(co7+co6)+co5+co4cs=(co3+co2)+co1+co0 figure 19 2 x 2 x 32 2 x 2 x 32 192 cs=2(co7+co6)+co5+co4cs=(co3+co2)+co1+co0 figure 20 4 x 1 x 32 4 x 1 x 32 480 cs=8co7+4co6+2co5+co4cs= 8co3+4co2+2co1+co0 table 11. register contents fo r 1 x 256 correlator with equal weighting a0-2 dcont0-7 notes 001 00000000 1 256-tap correlator: 1 x 256 window con- figuration, reference loaded from dref7, eight stages weighted equally, din 7 and dout7 are the data input and output, re- spectively. 010 000000f00 offset register a = 0. 011 00000000 100 00000000 programmable delay = 0. 101 00000000 offset register b = 0 (loading of this reg- ister optional in this mode). 110 00000000 hsp45256
14 the loading of the reference and mask registers may be done simultaneously by setting a0-2 = 000, setting the dref and dcont inputs to their proper values and pulsing rlo ad and clo ad low. in this con?guration, dref7 loads the reference data and dcont7 loads the mask information; both sets of data are loaded serially. it will take 256 load pulses ( rlo ad) to load the reference array, and 256 clo ad pulses to load the mask array. upon completion of the mask and register loading, txfr is pulsed low, which transfers the reference and control data from the preload registers to the reference and mask registers, updating the data that will be used in the correlation. reference and mask data can be loaded more quickly by con?guring the correlator as an 8 row by 32 sample array, loading the bits eight at a time, then changing the con?guration back to 1 x 256 to perform the correlation. other 1-bit con?gurations 1-bit, dual row, 128 sample con?guration 7 6 5 4 3 2 1 0 ref <7> data <7> refout <7> dataout <7> cs = (co7+co6+co5+co4+co3+co2+co1+co0) figure 5. 1-bit, 1 row of 256 taps 7 6 5 4 3 2 1 0 ref <7> data <7> refout <3> dataout <3> cs = (co7+co6+co5+co4+co3+co2+co1+co0) refout <7> dataout <7> ref <3> data <3> figure 6. 1-bit, 2 rows of 128 taps 1-bit, quad row, 64 sample con?guration figure 7. 1-bit, 4 rows of 64 taps 1-bit, octal row, 32 sample con?guration figure 8. 1-bit, 8 rows of 32 taps 2-bit con?gurations 2-bit, single row, 128 sample con?guration figure 9. 2 bits, 1 row of 128 taps 7 6 5 4 3 2 1 0 ref <7> data <7> refout <1> dataout <1> cs = (co7+co6+co5+co4+co3+co2+co1+co0) refout <5> dataout <5> ref <3> data <3> refout <7> dataout <7> ref <5> data <5> refout <3> dataout <3> ref <1> data <1> 7 6 5 4 3 2 1 0 ref <7> data <7> refout <0> dataout <0> cs = (co7+co6+co5+co4+co3+co2+co1+co0) refout <4> dataout <4> ref <3> data <3> refout <6> dataout <6> ref <5> data <5> refout <2> dataout <2> ref <1> data <1> refout <7> dataout <7> refout <5> dataout <5> refout <3> dataout <3> refout <1> dataout <1> ref <6> data <6> ref <4> data <4> ref <2> data <2> ref <0> data <0> 7 6 5 4 3 2 1 0 ref <7> data <7> refout <3> dataout <3> cs = 2(co7+co6+co5+co4)+(co3+co2+co1+co0) refout <7> dataout <7> data <3> hsp45256
15 2-bit data, dual row, 64 samples figure 10. 2-bits, 2 rows of 64 taps 2-bit, quad row, 32 sample con?guration figure 11. 2-bits, 4 rows of 32 taps 4-bit con?gurations 4-bit, single row, 64 sample con?guration figure 12. 4-bits, 1 row of 64 taps 4-bit dual row, 32 sample con?gurations figure 13. 4 bits, 2 rows of 32 taps 7 6 5 4 3 2 1 0 ref <7> data <7> refout <1> dataout <1> cs = 2(co7+co6+co5+co4)+(co3+co2+co1+co0) refout <5> dataout <5> data <3> refout <7> dataout <7> refout <3> dataout <3> data <1> ref <5> data <5> 7 6 5 4 3 2 1 0 ref <7> data <7> refout <0> dataout <0> cs = 2(co7+co6+co5+co4)+(co3+co2+co1+co0) refout <4> dataout <4> data <3> refout <6> dataout <6> refout <2> dataout <2> data <1> ref <6> data <6> data <2> data <0> refout <7> dataout <7> refout <5> dataout <5> refout <3> dataout <3> refout <1> dataout <1> ref <5> data <5> ref <4> data <4> 7 6 5 4 3 2 1 0 ref <7> data <7> refout <1> dataout <1> cs = 8(co7+co6)+4(co5+co4)+2(co3+co2)+(co1+co0) refout <5> dataout <5> data <3> refout <7> dataout <7> refout <3> dataout <3> data <1> data <5> 7 6 5 4 3 2 1 0 ref <7> data <7> refout <0> dataout <0> cs = 8(co7+co6)+4(co5+co4)+2(co3+co2)+(co1+co0) refout <4> dataout <4> data <3> refout <6> dataout <6> refout <2> dataout <2> data <1> data <5> ref <6> data <6> data <4> data <2> data <0> refout <7> dataout <7> refout <5> dataout <5> refout <3> dataout <3> refout <1> dataout <1> hsp45256
16 8-bit configurations 8-bit data, single row, 32 sample configurations an 8 x 32 correlation also requires only 1 hsp45256. to initialize the correlator, all the reference bits, control bits, the value of the programmable delay, and the window configuration must be specified. table 12 details these settings. again, the loading of the reference and mask registers can be done simultaneously. due to the programming initialization, dref0-7 are used to load the reference data 8- bits at a time. it will take 32 load pulses each of rlo ad and clo ad to load both arrays. upon completion of the mask and register loading, txfr is pulsed low, which transfers the reference and control data from the preload registers to the registers that store the active data. this con?guration performs correlation of an 8-bit number with a 1-bit reference. each byte out of the correlation array gives an 8-bit level of con?dence that the data corresponds to the reference. the correlation score is the sum of these con?dence levels. table 12. register loading for 8 x 32 correlator with binary weighting a0-2 dcont0-7 notes 001 00001111 1 256-tap correlator; 8 x 32 window con?gu- ration, 8-bit data stream; reference register is loaded from dref7 for all stages. correlator score = (128 x co7) + (64 x co3) + (32 x co5) + (16 x co1) + (8 x co6) + (4 x co4) + (2 x co2) + co0. 010 00000000 offset register a = 0000000010000. 011 00010000 100 00000000 programmable delay = 0. 101 00000000 offset register b = 0 (loading optional in this mode). 110 00000000 7 6 5 4 3 2 1 0 ref <7> data <7> refout <0> dataout <0> cs = 128co7+64co6+32co5+16co4+8co3+4co2+2co1+co0 refout <4> dataout <4> data <3> refout <6> dataout <6> refout <2> dataout <2> data <1> data <5> data <6> data <4> data <2> data <0> refout <7> dataout <7> refout <5> dataout <5> refout <3> dataout <3> refout <1> dataout <1> figure 14. 8 bits, 1 row of 32 taps hsp45256
17 dual correlator con?gurations 1-bit, single row, 128 sample con?guration figure 15. dual 1-bit, 1 row of 128 taps 1-bit, dual row, 64 sample con?guration figure 16. 1-bit, 2 rows of 64 taps 1-bit, quad row, 32 sample con?guration figure 17. 1-bit, 4 rows of 32 taps 7 6 5 4 ref <7> data <7> dataout <7> csa = (co7+co6+co5+co4); (casout) 3 2 1 0 ref <3> data <3> dataout <3> csb = (co3+co2+co1+co0); (auxout) 7 6 5 4 ref <7> data <7> dataout <5> csa = (co7+co6+co5+co4); (casout) dataout <7> ref <5> data <5> 3 2 1 0 ref <3> data <3> dataout <1> csb = (co3+co2+co1+co0); (auxout) dataout <3> ref <1> data <1> 7 6 5 4 ref <7> data <7> dataout <4> csa = (co7+co6+co5+co4); (casout) dataout <6> ref <5> data <5> dataout <7> ref <6> data <6> dataout <5> ref <4> data <4> 3 2 1 0 ref <3> data <3> dataout <0> csb = (co3+co2+co1+co0); (auxout) dataout <2> ref <1> data <1> dataout <3> ref <2> data <2> dataout <1> ref <0> data <0> hsp45256
18 2-bit, dual row, 64 sample con?guration dual 2 x 64 correlators require only one hsp45256. to initialize the correlator, all the reference bits, control bits, the delay value of the variable delay, and the window configuration must be specified. table 13 details the settings for the 2-bit dual row, 64 sample configuration. in this example, each of the dual correlators compares 2-bit data to a 1-bit reference. it will take 64 load pulses ( rlo ad/ clo ad) to completely load the reference and mask registers in the array. the programmable delay must be set to 0 for the output of the two correlators to be aligned. 7 6 5 4 3 2 1 0 ref <7> data <7> csa = 2(co7+co6)+co5+co4); (casout) ref <3> data <3> data <5> data <1> dataout <7> dataout <5> dataout <3> dataout <1> csb = 2(co3+co2)+co1+co0); (auxout) figure 18. 2-bits, 1 row of 64 taps table 13. register loading for dual 2 x 64 correlators with equal weighting ao-2 dcont0-7 notes 001 00010110 dual correlators: each 2 bit data, 64 taps; reference register for correlation a is loaded from dref7 and dref5, the reference register for correlator b is loaded from dref3 and dref1. correlator #1 = 2x c07 + 2 x co6 + co5 + co4, correlator #2 = 2 x co3 + 2x co2 + co1 + co0. 010 00000000 offset register a = 0000000010000. 011 00010000 100 00000000 programmable delay = 0. 101 00000000 offset register b = 0. 110 00000000 2-bit, dual row, 32 sample con?guration figure 19. 2-bits, 2 rows of 32 taps 4-bit, single row, 32 sample con?guration figure 20. 4-bits, 1 row of 32 taps 7 6 5 4 3 2 1 0 ref <7> data <7> dataout <0> ref <3> data <3> ref <6> data <6> dataout <2> data <1> dataout <7> dataout <5> dataout <3> dataout <1> ref <2> data <2> data <0> csa = 2(co7+co6)+co5+co4); (casout) csb = 2(co3+co2)+co1+co0); (auxout) dataout <6> dataout <4> data <5> data <4> 7 6 5 4 ref <7> data <7> dataout <4> csa = 8(co7)+4(co6)+2(co5)+(co4); (casout) dataout <5> data <5> dataout <7> dataout <5> data <4> data <6> 3 2 1 0 ref <3> data <3> dataout <0> csb = 8(co3)+4(co2)+2(co1)+(co0); (auxout) dataout <2> data <1> dataout <3> dataout <1> data <0> data <2> hsp45256
19 cascading multiple correlator devices correlators can be cascaded in either a serial or parallel fashion. longer correlations can be achieved by connecting several correlators together as shown in figures 21- 23. in figure 21, each correlator is in a one data bit, one row, 256 tap con?guration. the number of bits of signi?cance at the casout output of each correlator builds up from one correlation to the next, that is, the maximum score out of the ?rst correlator is 256, the maximum output of the second correlator is 512, etc. in this con?guration, the maximum length of the correlation is 4096. this would be implemented with 16 hsp45256s. the programmable delay register in the ?rst correlator would be set for one delay, the second would be set for two, and so on, with the ?nal hsp45256 being set for a delay of 16. correlations of more bits can be calculated by connecting casout of each chip to the casin of the following chip (figure 21). the data on the casout lines accumulates in a similar manner as in the 1 x 256 mode, except that the maximum output of the ?rst correlator is decimal 960, (hexadecimal 3c0); in the general case, the maximum number of correlators that can be cascaded in this manner is eight, since the maximum output of the last one would be 1e00, which nearly uses up the 13-bit range of the cascade summer. more parts could be cascaded together if some bits are to be masked out or if the user has a prior knowledge of the maximum value of the correlation score. as before, the delay in the ?rst correlator would be set to one, the second correlator would be set for a delay of two, and so on. multiple hsp45256s can be cascaded for two dimensional one bit data (figure 22). the maximum output for each chip is the same as in the 1 x 256 case; the only difference is in the manner in which the correlators are connected. the programmable delay registers would be set as before. figure 21. 1-bit, 1024 sample configuration figure 22. 4-bit, 256 sample configuration figure 23. 1-bit, 32 x 32 window configuration correlator score output din7 casin0-12 casout0-12 dout7 data input din7 casin0-12 casout0-12 dout7 din7 casin0-12 casout0-12 dout7 din7 casin0-12 casout0-12 dout7 correlator score output din7, 5, 3, 1 casin0-12 casout0-12 dout7, 5, 3, 1 data input din7, 5, 3, 1 casin0-12 casout0-12 dout7, 5, 3, 1 din7, 5, 3, 1 casin0-12 casout0-12 dout7, 5, 3, 1 din7, 5, 3, 1 casin0-12 casout0-12 dout7, 5, 3, 1 correlator score output din0-7 casin0-12 casout0-12 data input din0-7 casin0-12 casout0-12 din0-7 casin0-12 casout0-12 din0-7 casin0-12 casout0-12 rows 0 - 7 data input rows 8 - 15 data input rows 16 - 23 data input rows 24 - 31 hsp45256
20 reloading data during operation rlo ad and clo ad are asynchronous signals that are designed to be driven by the memory interface signals of a microprocessor. txfr is synchronized to clk so that the mask or reference data is updated on a speci?c clock cycle. in the normal mode of operation, the user loads the reference and mask memories, then pulses txfr to use that data. the correlator uses the new mask or reference information immediately. loading of the reference and mask data remains asynchronous as long as there is at least one cycle of clk between the rising edge of rlo ad or clo ad and the txfr pulse. if the system timing makes it necessary for txfr and rlo ad and/or clo ad to be active during the same clock cycle, then they must be treated as synchronous signals; the timing for this case is shown in figure 24 and given in the ac timing speci?cations (t thcl and t cllh ). in this example, data is loaded during clock cycle 1 and transferred on the rising edge of clk that occurs in clock cycle two. another set of data is loaded during clock cycle 2, which will be transferred by a later txfr pulse. the sequence of events is as follows: 1. in clock cycle 1, txfr becomes active at least t th nano- seconds after the rising edge of clk. 2. rload and/or clo ad pulses low; the timing is not critical as long as its rising edge occurs before the end of clock cycle 1. if this condition is not met, it is undeter- mined whether the data loaded by this pulse will be trans- ferred by the current txfr pulse. 3. the rising edge of txfr occurs while clk is high during clock cycle 2. the margin between the rising edge of txfr and the falling edge of clk is de?ned by t thcl . 4. rlo ad and/or clo ad pulses low. the rising edge of rlo ad and clo ad must occur after the falling edge of clk. the margin between the two is de?ned by t cllh . the time from the rising edge of txfr to the falling edge of clk must be greater than t thcl , and the time from the falling edge of clk to the rising edge of rlo ad or clo ad must be greater than t s . if this timing is violated, the data being transferred by the txfr pulse shown may or may not include the data loaded in clock cycle 2. clk txfr rlo ad, clo ad clock cycle 1 clock cycle 2 figure 24. loading and transferring data during the same clock cycle t th 1. 2. t thcl 3. t cllh 4. hsp45256
21 absolute maximum ratings thermal information supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8.0v input, output or i/o voltage . . . . . . . . . . . . gnd -0.5v to v cc +0.5v esd classi?cation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . class 1 operating conditions voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.75v to +5.25v temperature range commercial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 o c to 70 o c industrial. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40 o c to 85 o c thermal resistance (typical, note 1) q ja ( o c/w) q jc ( o c/w) plcc package. . . . . . . . . . . . . . . . . . . 34 - pga package. . . . . . . . . . . . . . . . . . . . 36 10 maximum package power dissipation commercial pga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2.9w commercial plcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2.3w industrial plcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.9w maximum storage temperature range . . . . . . . . . . -65 o c to 150 o c maximum junction temperature plcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150 o c pga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175 o c maximum lead temperature (soldering 10s) . . . . . . . . . . . . .300 o c gate count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13,000 gates caution: stresses above those listed in absolute maximum ratings may cause permanent damage to the device. this is a stress only rating and operatio nofthe device at these or any other conditions above those indicated in the operational sections of this speci?cation is not implied. note: 1. q ja is measured with the component mounted on an evaluation pc board in free air. dc electrical speci?cations parameter symbol test conditions min max units logical one input voltage v ih v cc = 5.25v 2.0 - v logical zero input voltage v il v cc = 4.75v - 0.8 v high level clock input v ihc v cc = 5.25v 3.0 - v low level clock input v ilc v cc = 4.75v - 0.8 v output high voltage v oh i oh = 400 m a, v cc = 4.75v 2.6 - v output low voltage v ol i ol = +2.0ma, v cc = 4.75v - 0.4 v input leakage current i i v in = v cc or gnd, v cc = 5.25v -10 10 m a output leakage current i o v out = v cc or gnd, v cc = 5.25v -10 10 m a standby power supply current i ccsb v in = v cc or gnd, v cc = 5.25v - 500 m a operating power supply current i ccop f = 25.6mhz, v in = v cc or gnd, v cc = 5.25v, note 2, 4 - 179 ma capacitance t a = 25 o c, note 3 parameter symbol min max units test conditions input capacitance c in - 10 pf frequency = 1mhz, v cc = open all measurements are referenced to device ground. output capacitance c o -10pf notes: 2. power supply current is proportional to operating frequency. typical rating for i ccop is 7ma/mhz. 3. not tested, but characterized at initial design and at major process/design changes. 4. output load per test load circuit and c l = 40pf. ac electrical speci?cations v cc = 5.0v 5%, t a = 0 o c to 70 o c, t a = -40 o c to 85 o c, note 5 parameter symbol notes 33mhz 25.6mhz units min max min max clk period t cp 30-39-ns clk high t ch 12-15-ns clk low t cl 12-15-ns hsp45256
22 test load circuit set-up time din to clk high t ds 12-13-ns hold time clk high to din t dh 0-0-ns txfr set-up time t ts 12-13-ns txfr hold time t th 0-0-ns output delay dout, auxout, casout t do - 15 - 20 ns clo ad cycle time t clc 30-39-ns clo ad high t clh 12-15-ns clo ad low t cll 12-15-ns set-up time, a to rlo ad, clo ad t as 12-13-ns hold time, rlo ad, clo ad to a t ah 0-0-ns rlo ad cycle time t rlc 30-39-ns rlo ad high t rlh 12-15-ns rlo ad low t rll 12-15-ns set-up time, dcont to clo ad t dcs 12-13-ns hold time, clo ad to dcont t dch 0-0-ns set-up time, dref to rlo ad t rs 12-13-ns hold time, rlo ad to dref t rh 0-0-ns output enable time t oe - 15 - 15 ns output disable time t od note 6 - 15 - 15 ns output rise, fall time t rf note 6 - 6 6 ns txfr high to clk low t thcl note 6 3 - 3 - ns clk low to rlo ad, clo ad high t cllh note 6 1 - 1 - ns notes: 5. ac testing is performed as follows: input levels (clk input) 4.0v and 0v; input levels (all other inputs) 0v and 3.0v; timing reference levels (clk) 2.0v; all others 1.5v. output load per test load circuit with c l = 40pf. output transition is measured at v oh > 1.5v and v ol < 1.5v. 6. controlled via design or process parameters and not directly tested. characterized upon initial design and after major process and/or design changes. ac electrical speci?cations v cc = 5.0v 5%, t a = 0 o c to 70 o c, t a = -40 o c to 85 o c, note 5 (continued) parameter symbol notes 33mhz 25.6mhz units min max min max dut equivalent circuit 1.5v i ol i oh ? c l includes stray and jig ? s 1 capacitance switch s 1 open for i ccsb and i ccop test hsp45256
23 all intersil semiconductor products are manufactured, assembled and tested under iso9000 quality systems certi?cation. intersil semiconductor products are sold by description only. intersil corporation reserves the right to make changes in circuit design and/or spec ifications at any time with- out notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is b elieved to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of th ird parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see web site http://www.intersil.com timing waveforms figure 25. input, output timing figure 26. control input timing figure 27. reference input timing figure 28. output timing figure 29. transfer, load timing when both occur on a single cycle clk din0-7 txfr dout0-7 casout0-12, auxout0-8 t cp t cl t ch t dh t ds t ts t th t ts t do clo ad a0-2 t clc t cll t clh t ah t as dcont0-7 t ch t cs dlo ad a0-2 t rlc t rlh t rll t ah t as dref0-7 t rh t rs t r , t f 2.0v 0.8v t oe 1.7v 1.3v oea, oec t od auxout0-8 casout0-12 dout0-7, casout0-12, auxout0-8 t thcl t cllh clk txfr rlo ad, clo ad hsp45256

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